|ARM cache management via CP15 register C7|
Wednesday, September 30, 2015
Cache management overview across ARM architectures
I've recently run into troubles caused by subtle differences in how the different ARM subarchitectures or their implementations manage caches. Sometimes an implementation does not implement what its respective subarchitecture mandates (or rather suggests), sometimes it implements more. ARMv4 to ARMv6 are quite similar, but ARMv7-A is completely different, because of the possibility to have multiple levels of caches across multiple processors and the new concepts of points of coherence and unification that come with it. When dealing with these differences, I wished there was a simple table that would tell me what subarchitecture supports what features, but there wasn't... Until now. The following chart depicts the situation for ARM processors and subarchitectures supported by HelenOS.